In contrast to the majority of video display devices which allow the user various modes for the whole display, Nick allows many different modes in the same display frame
The Nick Chip is capable of addressing 64K of memory, referred to as the
"Video RAM", which consists of the four segments
0FCh to 0FFh. Thus the Nick Chip can address
any of the internal 64K of RAM in the
Enterprise 64, but
cannot address any additional RAM which is added.
The Nick Chip addresses this 64K directly, without going through the
Dave Chip paging registers. For example it will always
address the start of segments FDh as address
04000h, regardless of where the Z80 is seeing this segment,
indeed it may not even be paged in. Care must be taken to avoid confusing
these video addresses with Z80 addresses.
The display generated by the Nick Chip is controlled by a block of data in video RAM referred to as the line parameter table. This consists of a series of line parameter blocks, each of wich is 16 bytes long. The line parameter table can be positioned on any 16byte boundary in video RAM and can contain any number of line parameter blocks. The user simply loads the address of the start of the line parameter table into a register in the Nick Chip and the display is then generated automatically.
Each line parameter block controls a section of the screen called a mode line, and contains data to indicate what type of display this mode line is and the address of the video RAM containing the screen data. A mode line may consist of any number of scanlines from 1 to 256. The Nick Chip generates the required number of scanlines for the first mode line and then goes on to the next mode line, reading the next line parameter block and so on.
The last line parameter block in the table must have a particular bit set to indicate that when this mode line is finished the Nick Chip should start again at the beginning of the line parameter table. Normally the total number of scanlines in all the mode lines in the table would be 312, so that each scan of the line parameter table generates one TV frame. However if interlacing or other special effects are required, the line parameter table may be larger.
The Nick Chip generates all the horizontal timing itself so that all scanlines will be 64µs long and have the correct blanking, sync and colour burst signals. However the vertical timing is under the control of the programmer. The line parameter table must contain suitable line parameter blocks to generate the vertical blanking and sync signals.
The address of the start of the line parameter table must be loaded into
the Nick Chip in order to generate a display. Only the top twelve bits
are loaded since it must always be on a 16byte boundary, and two
separate 8bit registers (LPL and
LPH) in the Nick Chip are used.
The user can switch to a different display by simply loading a new line parameter base pointer value. The Nick Chip will finish its current scan of the line parameter table and the reload the new value and start on the new line parameter table. There can be a problem if the Nick Chip happens to be in the middle of a reload when the user writes out the new address. Its is possible for the Nick Chip to reload half of the old address and half of the new one, and start scanning the wrong section of memory. To avoid this problem, any such reloading of the line parameter base pointer should be synchronised with a video interrupt to ensure that the reload is not in progress. Video interrupts are described later.
When the Nick Chip is switched on it will initially be scanning garbage
until a base pointer is loaded. However when a new value is loaded it will
not be used until the Nick Chip reads a line parameter block with the
reload bit set, causing a delay before the display appears
correctly. To avoid this problem, two otherwise unused bits in
LPH are used to allow a forced reload
of the line parameter base pointer. In normal use these bits are both set
to one. To force a reload the following procedure must be followed.
LPL.
LPH, bits
6 & 7 clear.
Each line parameter block consists of 16 bytes which the Nick Chip reads in during the horizontal blanking time at the start of a scanline. The sixteen bytes are:
0 1 2 3 4 5 6 7 8 ·· 15 +----+----+----+----+-----+-----+-----+-----+----- // -----+ | SC | MB | LM | RM | LD1L LD1H | LD2L LD2H | COL0 ·· COL7 | +----+----+----+----+-----+-----+-----+-----+----- // -----+
b7 b6 b5 b4 b3 b2 b1 b0 +------+------+------+------+----+----+----+--------+ | VINT | COLOUR MODE | VRES | VIDEO MODE | RELOAD | +------+------+------+------+----+----+----+--------+
00 - 2colour mode
01 - 4colour mode
10 - 16colour mode
11 - 256colour mode
000 - vsync mode
001 - pixel mode
010 - attribute mode
011 - ch256 mode
100 - ch128 mode
101 - ch64 mode
110 - unused
111 - lpixel mode
b0···b5 - Left margin of display.
b6 - LSBALT \ Control alternate colours in
b7 - MSBALT / 2-colour graphics modes.
b0···b5 - Right margin of display.
b6 - ALTIND1 \ Control alternate colours in
b7 - ALTIND0 / 2-colour character modes.
COL7
Each horizontal scanline is divided up into 57 slots, with the Nick Chip able to read two bytes from video RAM in each slot. The first eight slots are used to read in the line parameter block, and the last three are used to provide refresh of the video RAM. This leaves 46 slots which are available for display.
The left and right margin bytes in the mode line define which slot number the active display starts and finishes on respectively. The area outside these margins will be border colour, apart from the necessary horizontal blanking and sync. In practice, because of TV overscan, some of the slots will be off the screen, and a practical limit to the display width is 52 slots, using a left margin value of 10 and a right margin of 52.
In the active section of display between the margins, the Nick Chip reads bytes from video RAM in a way depending on the video mode and produces either one or two bytes for display in each slot. The way these bytes are converted into pixels depends on the colour mode selected.
If the right margin is set to a lower value than the left margin then the entire mode line will be border colour, with no active display. Note that the margin positions have special meaning in vsync mode where they are used to generate the vertical sync pulses. This is described in the section on vertical synchronisation.
The colour mode controls the way in which display bytes are converted into colours. The Nick Chip has eight colour outputs, allowing 256 different colours to be generated. In 256colour mode, each byte read from video RAM is simply output directly as a colour byte. In all other colour modes (2, 4 and 16), the display byte is splitup into a number of pixels, and the values of these pixels are used to select one of upto sixteen palette colours to be displayed. The translation of colour bytes into actual colours is explained in a later section.
The first 8 palette colours (0...7) are defined by the last 8 bytes in the
line parameter block. Thus these can be any eight colouts from the total
of 256, and can be chosen seperately fro each mode line. The remaining
eight colours (in the range 8...15) are generated by taking the bottom 3
bits of the palette colour number, and forming a complete colour byte by
putting five bits from the FIXBIAS
register in the top five
bits. The FIXBIAS register is a single register in the Nick
Chip (port 080h) which is also used for various other
functions described later. Thus it is possible to choose any of 32 groups
of 8 colours for the remaining palette colours, but they will be the same
for the whole screen (unless the FIXBIAS register is changed
rapidly under interrupt control).
The translation of display bytes into pixels is different for the three palette colour modes. Note particulary the ordering of bits in the pixels for 16colour mode.
+----+----+----+----+----+----+----+----+ | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | +----+----+----+----+----+----+----+----+
+---------+---------+---------+---------+ | b3,b7 | b2,b6 | b1,b5 | b0,b4 | +---------+---------+---------+---------+
+-------------------+-------------------+ | b1,b5,b3,b7 | b0,b4,b2,b6 | +-------------------+-------------------+
In pixel and lpixel graphics modes the LD2
pointer value is not used at all. The LD1 pointer points at
the address in video RAM of the first byte to be displayed. Bytes are
read in sequence from video RAM starting from the left margin and
continuing to the right margin of each scanline. If VRES is
set then the next scanline of this modeline continues at the next byte in
video RAM, if VRES is clear then the LD1
pointer is reloaded so the same data will be displayed on each scanline.
This allows memory to be saved by reducing vertical resolution.
The bytes read from video RAM are translated according to the colour mode as described above. The only difference between pixel and lpixel mode is that in pixel mode two bytes are read in each slot, whereas in lpixel mode only one byte is read. Thus lpixel mode only has half the horizontal resolution, and only uses half the amount of RAM.
Two special control bits
are provided for use with 2colour pixel
graphics modes. These are MSBALT and LSBALT
which are in the top two bits of the left margin byte. They are provided
for simulating high resolution text modes in PIXEL mode, and allow
different coloured characters to be displayed.
If MSBALT is set then bit 7 of all display bytes will be forced to zero before displaying. If bit 7 was set then palette colours 2 and 3 will be used instead of colours 0 and 1 for the remaining pixels in this byte.
If LSBALT is set then bit 0 of all display bytes will be forced to zero before displaying. If bit 0 was set then palette colours 4...7 will be used instead of palette colours 0...3 for the remaining pixels in this byte.
In the character modes, LD2 points to a character font and
LD1 points to the character codes to be displayed. One
character code is read, and the font byte for it fetched, in each slot,
allowing up to 42 characters per line. VRES should always be
clear for character modes. The three character modes vary only in the
number of characters in the font, and therefore the amount of RAM required
for the font. Ch128 will be used as an example in this
description, the other two modes follow trivially.
The font for ch128 mode must alway start on a 128byte
boundary, and the address stored in LD2 is in fact the font
address divided by 128 (thus the top 9 out of 16 bits). The remaining 7
bits of address are generated by the Nick Chip.
The first 128 bytes of the font are the display bytes for the top scanline
of each of the 128 characters. The next 128 bytes are the display bytes
for the second scanline and so on. There must be sufficient lines in the
font for the SC count in the line parameter block.
The character codes are read sequentially from the LD1
address and the appropriate display byte for the current scanline
obtained from the font. This display byte is translated into colours just
as in the pixel graphics modes, depending on the colour mode. For
producing ASCII type characters, 2colour mode is normally used but
other colour modes can be used for doing character based graphics, with
fewer pixels across each character.
Two control bits are provided to allow different coloured characters in
2colour text modes. These are ALTIND0 and
ALTIND1 which are the top two bits of the right margin byte.
These are particularly useful in 64 and 128 character modes when the top
bits of the character codes are not used.
If ALTIND1 is set then character codes with but 7 set will
use palette colours 2 and 3 instead of 0 and 1 for displaying this
character.
If ALTIND0 is set then character codes with bit 6 set will
use palette colours 4...7 instead 0...3 for displaying this character.
In attribute graphics mode, LD2 points to two colour bitmap
graphics data, and LD1 points to an area of cell based
graphics attributes. When using attribute mode, the colour mode should
always be set to 2colours, any other colour modes will have
unpredicatable results.
The pixel data is read in just the dame way as for 2colour pixel graphics mode, but the corresponding attribute byte defines which two palette colours should be used for displaying this single byte as below:
b7 b6 b5 b4 b3 b2 b1 b0
+----+----+----+----+----+----+----+----+
| Background colour | Foreground colour |
+----+----+----+----+----+----+----+----+
The correspondence between attribute bytes and pixel bytes depends on
VRES. If VRES is set then there is a one to one
correspondence, so the attribute data will take up the same amount of RAM
as the pixel data. If VRES is clear then the attribute data
will repeat for each scanline in the mode line. Thus each attribute byte
will correspond to a number of bytes vertically above one another, in the
same way as the character code corresponds to several lines in character
modes.
In vsync mode, no data is displayed on the screen, the video output is held at blanking level, and the margins define the start and end of the vertical sync pulse. Note also that colour burst is disabled during vsync lines.
During the active vertical sync period, the normal horizontal sync pulses will be inverted to prevent loss of horizontal sync. This is essential to produce a stable display.
A line parameter table must contain a sequence of line parameter blocks (LPB) to generate the correct vertical blanking and sync pulses. The recommended sequence is as follows, the last 12 bytes of each line parameter block should be zero so just the first four bytes are listed here.
+--------+--------+----+----+--//--+
| 256-3 | VBLANK | 63 | 0 | |
+--------+--------+----+----+--//--+
| 256-2 | VBLANK | 6 | 63 | |
+--------+--------+----+----+--//--+
| 256-1 | VBLANK | 63 | 32 | |
+--------+--------+----+----+--//--+
| 256-19 | PIXEL | 6 | 63 | |
+--------+--------+----+----+--//--+
The first of these LPBs gives three lines of blanking. Since the left margin is set to 63 which is never reached, the sync will not be turned on. The sync is turned on near the start of the second LPB, and remains on throughout this LPB because the right margin of 63 is never reached. The sync is turned off half way through the single scan line of the third LPB, giving 2.5 lines of sync. The fourth LPB provides nineteen more lines of blanking to make total of 25 lines, but in 2colour pixel mode so that the colour burst is reenabled. In this LPB the left margin is set to 6 to ensure that the border colour does not get displayed, the palette must be set to all black.
These LPBs make a total of 25 lines, leaving 287 lines left for the display. In practice, because of overscanning, it is not possible to use more than about 256 of these for display, the rest must provide top and bottom borders.
If an LPB has the VINT bit set in its MB byte,
then the VIRQ output of the Nick Chip will be made low for
the duration of that mode line. This is fed into the Dave
Chip where the start of the low pulse will cause a Z80 interrupt, assuming
that the video interrupts are enabled in the Dave Chip. details of how to
program the Dave Chip interrupts will be found in the Dave Chip
specification, but there are several points to note here.
Because the VIRQ output is held low for the duration of the
mode line, and because the Dave Chip input is edge triggered, the two
consecutive mode lines with VINT set will only cause one
interrupt because the second mode line will merely hold VIRQ
low without producing an edge. It is therefore necessary to have a mode
line with VINT clear to allow VIRQ to return
high before another interrupt can be generated.
Once the interrupt has occured, it is latched inside the Dave Chip and
must be reset there before interrupts can be reenabled. This is
normal practice with Dave Chip interrupts. If the interrupt is cleared
and interrupts are enabeld again before the VINT mode line
has finished, then another interrupt will not be
triggered because the Dave Chip input is edge triggered.
As described above, the Nick Chip generates a colour byte for each point on the screen, depencing on the video mode, colour mode, palette registers and so on. The 8bits of this colour value are converted into separate red, green and blue signals which are available on the monitor connector, and are also converted into a PAL encoded, UHF modulated signal which can be fed directly into a television.
Of the eight bits, there are three each for red and green and two bits for blue, thus allowing eight levels of red and green and four levels of blue. The layout of bits is:
b7 b6 b5 b4 b3 b2 b1 b0
+----+----+----+----+----+----+----+----+
| g0 | r0 | b0 | g1 | r1 | b1 | g2 | r2 |
+----+----+----+----+----+----+----+----+
The three bits for each colour are combined according to the formulas below. b0, g0 and r0 are the most significant bits of each colour, and the weighting for the blue levels takes into account teh fact that there are only four levels of blue.
total RED = ( r2 * 4 + r1 * 2 + r0 ) / 7
total GREEN = ( g2 * 4 + g1 * 2 + g0 ) / 7
total BLUE = ( b1 * 2 + b0 ) / 3
Z80 port numbers 080h to 08Fh reserved for Nick
Chip registers although only the first four of these (080h to
083h) are used at present. These registers are write only,
the values cannot be read back.
080h FIXBIAS
EC0-EC3,
allowing 16 colour sprites to be implemented. The external
colour will only be selected when the
/EXTC input
is low and the display is active (not border)
EC0-EC3 always select the corresponding
palette colour.
EC0-EC3 select the corresponding palette
colour if the internal display is generating a palette
colour in the range COL8-COL15.
EC0-EC3 select the corresponding palette
colour if the internal display is generating a palette
colour in the range COL8-COL15
or the external colour is in the range
COL0-COL7 (EC3 low).
EC0-EC3 select the corresponding palette
colour if the internal display is generating a palette
colour in the range COL8-COL15
or the external colour is in the range
COL0-COL3 or COL8-COL11
(EC2 low).
VC1 output of the Nick Chip. Set it to disable the
internal speaker in the
Enterprise.081h BORDER
082h LPL
A4..A11) of the line parameter
base pointer. The lowest four bits of the address are generated by
the Nick Chip.
083h LPH
A12..A15) of the line
parameter base pointer.
David Bouman (dsbouma@cs.vu.nl)
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